1. Field of the Invention
The present invention relates to a semiconductor device having a semiconductor chip and electrode terminals molded together with a sealing resin and a method of manufacturing the same.
2. Description of the Prior Art
The semiconductor device of conventional design will be discussed with reference to FIGS. 30A to 32. The semiconductor device 50a shown in FIG. 30A is disclosed in the Japanese Laid-open Patent Publication No. 3-94459 and is of a structure wherein a semiconductor chip 3 is mounted on a die pad 51, and wire pads 52 are spaced from the die pad 51 and connected with the semiconductor chip 3 through respective wires 4, both of said pads 51 and 52 being sealed by a synthetic resin 5. More specifically, the semiconductor chip 3 is bonded to the die pad 51 by means of a die bond material 2, and bump 53 are added to the wire pads 52.
The semiconductor device 5a disclosed in the publication No. 3-944459 is manufactured in the following processes. In the first place, as shown in FIGS. 31A and 31B, semiconductor chips are mounted on a metallic base substrate provided with die pads and wire pads and manufactured in a manner as shown by the flowchart of FIG. 32. This is followed by connection of the semiconductor chips with the wire pads with wires made from gold or other materials. Then, the semiconductor chips and the chip carrying surface of the metallic base substrate are sealed by a resinous materials. By doing so, the semiconductor devices are formed on the metallic base substrate 60 as shown in FIGS. 31A and 31B. Then a portion of the metallic base substrate 60 other than areas where the semiconductor devices have been formed is subsequently removed by etching to thereby complete fabrication of the individual semiconductor devices 50a.
The publication No. 3-944459 discloses an alternative method which comprises preparing a transfer film including a base film and a metallic layer of, for example, copper formed on the base film through a peel-off layer intervening therebetween, bonding semiconductor chips to the transfer film by the use of a die bonding material, connecting the semiconductor chips with the metallic layer by resin, through wires such as gold wires, sealing the semiconductor chips and a chip carrying surface of the metallic layer, and removing the base film by etching or peeling to thereby complete the individual semiconductor devices with each having both die and wire pads.
According to the publication No. 3-944459, in view of the fact that during the manufacture the metallic base substrate 60 or the base film is etched off, the metallic base substrate 60 or the base film cannot be reused, resulting in an increase in the cost of manufacture. Also, the etching process requires a relatively long processing time and a relatively high processing cost resulting in lower production levels. In addition, the etching process requires the use of an alkaline solvent and, a flushing of water, accompanied by lowering of the bondability between the sealing resin 5 and the external electrodes 35. This turn brings about reduction in reliability of the semiconductor device.
Even using the method in which the base film is peeled off, the base film is damaged or otherwise deformed and, therefore, no reuse is possible with the transfer film once used, resulting in an increase in the cost of manufacturing. Moreover, a minute uneven surface of 1 to 2 .mu.m of an electrolyte copper foil which is the metallic layer on the base film tends to constitute a cause of reduction in bondability between the metallic layer and the sealing resin 5 by an anchoring effect, resulting in reduction in reliability of the semiconductor device.
Furthermore, in the prior method of manufacturing semiconductor, since each of the semiconductor devices 50a are sealed to the metallic base substrate 60, the metallic base substrate 60 needs a proper space 60 between the neighboring semiconductor devices 50a, therefore, the number of the semiconductor devices 50a that can be manufactured on a given surface area of the metallic base substrate 60 is limited, thereby posing a problem associated with productivity.
Another prior art semiconductor device 50b shown in FIG. 30B is fabricated according to a method disclosed in, for example, the Japanese Laid-open Patent Publication No. 8-115991. The semiconductor device 50b includes a semiconductor chip 3 mounted on a lead frame having inner layers 33, 34a and 34b formed of materials such as nickel by the use of a evaporation technique or a plating technique utilizing a metal masking aperture and having a cladding 36 of a solder plating. More specifically, the semiconductor chip 3 is sealed at one side thereof by a resinous material S. The portion of the lead frame where no sealing resin is deposited, and other than an area where external electrodes 35 are formed, is covered by a solder resist 38.
The publication No. 8-115991 also discloses the lead frame provided with a cladding 36 of solder plating formed by press work.
According to the publication No. 8-115991, in the step of manufacturing semiconductor 50b, the formation of the inner layers 33, 34a and 34b of, for example, nickel, and the solder plated cladding 36 by the use of the evaporation technique or the plating technique utilizing the metal masking aperture requires a relatively long time, bringing about the problem of a reduction in productivity. Also, the formation of the lead frame by the use of press work requires the use of an expensive mold for each of the eventually fabricated semiconductor devices.